signal can cause distortion tones that are audibly more objectionable than noise modulation that would otherwise occur for noise-like jitter. (See "Audibility of Jitter Errors.")

The measured results for the experimental interface imply a time constant of about 65ns. This is interesting in that the interface signal used in the experiments exhibited risetimes in the order of 10ns at the receiver input when observed using a high-bandwidth oscilloscope. However; a band-limitation at any stage in the interface will cause jitter in the embedded clock signal, even if the interface signal- transition edges are subsequently cleaned up. Every stage in the interface - transmitter, link, and receiver - is a possible source of band-limitation, and thus jitter. We that an equivalent time constant of 65ns within the ADIC IC was responsible for the jitter observed in the experiments.

Interface Noise: Besides increasing the (low) possibility of amplitude errors, interface noise can also be the cause of timing jitter in a band-limited interface. Consider a link with a time constant of RC, where, at the zero-crossing points, the rate of change of the received interface signal will be equal to Vd/RC (where Vd is the transmitter driving voltage). Thus, peak interface noise of vn results in a jitter noise of peak amplitude given by:

Equation 15:

tjnoise = RC | vn / Vd |

Hence, a peak interface noise 20dB below the driving voltage and a time constant of l00ns will result in I0ns peak jitter due to the noise source. This is of the same order of magnitude as the jitter due to inter-symbol interference tjRC given by Equation 11 and plotted in fig.13. In practice, jitter due to noise will be wideband, and hence will be largely attenuated by the PLL filter at the receiver. This behavior can be contrasted with jitter due to inter-symbol interference, which will not be heavily attenuated for moderate PLL cutoff frequencies. This argument is given weight by fig.21, which shows the measured jitter spectrum in the experimental receiver for constant audio data (ie, no inter-symbol interference). Here, the jitter is shown to be lower than for the measurements taken with CD-audio tone tracks transmitted over the interface (fig.19), even though the same noise-jitter mechanism is present in both circumstances. However; note that the noise-jitter mechanism can also cause with the recovered clock at the receiver output r the PLL, and all clock circuitry between the PLL and converter requires high-speed, low-noise characteristics.

Interface Slew-Rate Imbalance: Another jitter mechanism can cause problems with biphase-mark coded interface signals is asymmetrical slew rates across the link. If the receiver recovers the embedded interface clock by detecting transitions at every cell edge, as in our original detection model, the difference between the number of positive-going and negative-going detection transitions across a frame will depend upon the number of ones and zeros (and hence the audio word) transmitted. In the limit, jitter due to slew-rate imbalance will equal the difference between the negative- and positive-going (slew-limited) zero-crossing times. Consider an interface signal with positive- and negative-going slew rates (Vsr+ and Vsr-, respectively). The peak jitter due to slew-rate imbalance will

be:

Equation 16:

tjSR = |Vd| /2 | 1/|VSR+| - 1/|VSR-| |

Thus, for an interface signal detected using 74HC logic circuitry, where Vd = 2.5V and positive- and negative-going slew rates are 0.5V/ns and 1V/ns. respectively, then Equation 16 gives the peak jitter due to slew imbalance as 125ns. Moreover, since the ratio of positive to negative going cell edges is dependent upon the transmitted audio word value, the jitter is likely to have strong components at audio frequencies. 9

The problem of slew-rate imbalance interface jitter can be solved by only detecting interface transitions in one direction. This is the approach adopted in the SAA7274 ADIC used in the experimental receiver circuit, where monitoring the signal on pin 4 using an oscilloscope reveals that only negative going interface transitions are used to recover the embedded clock.

JITTER ERROR MODELS
To assess the consequences of jitter in a D/A conversion process, we require a DAC jitter-error model. Harris has developed an analytical model for jitter in ADCs,10 but the error mechanism in a DA process is different and depends upon the specific DAC architecture employed. In this section we present error models for two classes of DAC (these models axe essentially the same as those presented by Hawksford11).

First, we consider a Nyquist-sampling DAC with a sample-and-hold unit, in which each of the individual sample values input to the DAC are held until the next sample arrives; we term this a "100% sample DAC." Second, an "impulsive" D/A conversion process is considered, where consecutive output samples do not overlap. This model approximates a pulse-density modulation (PDM) conversion strategy as used by Philips in their oversampled and noise- shaped "Bitstream" converters. The error models' ac curacy is established by comparing simulated results against actual measurements on physical DACs where jitter has been purposely introduced into the interface. This is important: the error models are used to make predictions about the ity of jitter artifact. (See "Audibility of Jitter Errors.")

100% Sample DAC: A 100% sample DAC holds the value of a given sample at its output until a new sample arrives. Thus, timing error at the transition between adjacent samples results in a reconstructed analog signal an "error area" directly proportional to the product of the sample timing jitter and the difference between the sample values (fig2 3a). If we denote the normalized sample values as An and corresponding jitter values tjn, then if the jitterampli tude is small compared to the sampling period ts, we can form an error sequence en by scaling the error area by the sampling period:


9 It is possible that this kind of mechanism is responsible for the reported sound- quality differences between different families of logic chips.       --JA
10 S. Harris, 'The Effects of Sampling Clock Jitter on Nyquist Sampling Analog- to-Digital Converters, and on Oversampling Delta-Sigma ADCs, " JAES, July/August 1990, Vol.38, pp.537-542.
11 M.O. Hawksford, "Digital-to-Analog Converter with Low Inter-Sample Transition Distortion and Low Sensitivity to Sample Jitter and Transresistance Amplifier Slew Rate," presented at the 93rd AES Convention, San Francisco, October 1992.


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