with the result that. the interface time constant can be increased to 120ns before jitter audibility occurs. Finally, fig.38 compares the jitter errors from 100% and impulsive DACs, respectively, while replicating a 200Hz full-scale sinusoid from an interface with a l00ns time constant (the PLL filter is set to 1kHz, second-order). The higher jitter error from the impulsive model while reproducing l ow-counterparts.35

Clearly, the lower the PLUs bandwidth, the more wide band filter the digital interface link can tolerate. Our simple audibility model has not considered masking due to the audio signal itself, when this is taken into account it is evident that reducing the PLL break frequency has the additional benefit of narrowing the jitter-error skirt around the audio signal - hence making the skirt less audible. There is a clear analogy here to data-reduction systems in which efficient coding of audio signals places the error directly under the audio signal where, became of masking, it is least audible.36

The worst case for interface jitter audibility is when the receiver PLL has a high-jitter bandwidth; several ADIC integrated circuits on the market have jitter bandwidths up to 5kHz. 37 In the limit (no filter at all) white jitter noise of to 180ps peak amplitude and even less sinusoidal jitter not produce errors that rise above the audibility curve, more or less justifying the recommendations in AES11-1991. Similarly, we have seen that for no PLL filter, the interface time constant must be lower than 40ns or, equivalently, possess a bandwidth higher than 4MHz, a requirement which makes the performance offered by TosLink type optical interface links marginal.38 39

The revised professional interface standard AES3-199240 stipulates a reasonable upper limit of 30ns on the 10-90% risetime for correctly terminated interface transmitters, corresponding to a time constant of 14ns. However, we have seen that time constants need to be minimized in each part of the interface (transmitter, link, receiver), and that observing sharp rise and fall times at one point in the chain does not guarantee waveform fidelity elsewhere For example, our experimental receiver circuit suffers from a 65ns time constant associated with the ADIC IC used.

Reducing the Audibility of Interface Jitter Errors: We have shown that embedded clock jitter in a band-limited digital audio interface is fundamentally a problem due to the digital audio interface standard in its current form. In particular, the jitter signal is intimately linked with the Zero-One bit sum of the serially transmitted audio words; a lower Zero-One sum range would remit in reduced jitter.

One way of lowering the sum using the present interface standard is to pad the unused bits in the auxiliary data and low-bit sections of each subframe (see fig.2). For example,


35 Martin Colloms, Hi-Fi News & Record Review, March 1991, pp.69- 71.
36 M.A. Krasner, "The Critical Band Coder - DigitalEncoding of Speech Signals Based on the Perceptual Requirements of the Auditory System," Proceedings of the 1980 IEEE International Conference on Acoustics, Speech and Signal Processing, pp.327-331 (1980).
37 Crystal Semiconductor Corporation, CS8411/CS8412 Digital Audio Receiver Data Sheet, April 1991.
38 S. Sakura, S. Onobuchi, M. Ito, and S. Katagiri, "Fiber Optic Link for Digital Audio Interface," IEEE Trans. Consumer Electronics, August 1988, Vol.34, pp.667-669.
39 Toshiba Corporation, TosLink Fiber Optic Devices Catalog, 1990.
40 AES3-1992, "AES Recommended Practice for Digital Audio Engineering - Serial Transmission Formal: for Two-Channel Linearly Digital Audio Data," JAES, March 1992, Vol.40, pp.146-165.

with 16-bit audio words, the sum can be reduced from ±16 to ±8 by appropriately filling these unused bits according to the value of each transmitted audio word.41 A second option is to transmit one of the two audio channels supported by the interface out of phase, such that, for stereo program with a strong monaural component, the Zero-One sum is reduced.

However, although these techniques may reduce the absolute jitter level, we will still be left with the undesired high correlation between jitter and audio. In order to break this correlation, we must somehow randomize the sign structure of the transmitted bits, perhaps by modulating each bit sign with a known pseudo-random binary sequence, synchronized at the start of each interface block.

The AES/EBU-S/PDIF digital audio interface is now in widespread use; we are not likely to see a new interface standard welcomed by the majority of users for a considerable time. Accepting that jitter will occur in a band-limited interface, we must examine methods of reducing recovered clock jitter in receivers. Evidently the first step to take in minimizing interface jitter is to maximize the bandwidth of all components in the interface. However, there are limits to achieving high bandwidth at low cost, especially for long links, and conflicts with RFI may develop as rise and fall times become very fast. Alternately, the audibility of interface jitter in a conversion process can be reduced by making thereceiver PLL cutoff frequency as low as possible. But note that PLLs with


41 Could an advantageous change in the Zero-One sum be part of the reason such devices as the Audio Alchemy DTI.Pro 32 (reviewed in this issue by RH) and the Meridian 518 (reviewed in January '96, p.249) improve sound quality when set to increase word length?               - JA

bitmap image
(a)
bitmap image
Fig.38 Simulated interface jitter errors with low-frequency, audio signal, 200Hz at 0dBFS, 100ns interface time constant, and 2nd-order 1kHz PLL filter: a) 100% DAC (top); b) impulsive DAC (bottom).


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