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Fig.21 Measured jitter spectrum with receiver locked but no CD playing.

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Fig.22 Jitter measurement noise floor.

signals (fig20a-e). The simulations were obtained using the theory developed in "Interface Bandwidth Limitation" (above), with a minor change: the average jitter model out- lined above calculates the jitter based on interface signal transitions at every edge, while the Philips SAA7274 ADIC employed in the experimental receiver controls the PLL via timing errors at each negative-going transition. The simulation software was adjusted accordingly. Results were obtained using an interface time constant of 65ns and a first-order PLL loop filter with break frequency set to 1 kHz.

In general, the simulations show good agreement with the measured results; the only discrepancies appear as low- level tones in the measured jitter spectra at 230Hz 1.6kHz, and 2.1kHz. These tones are also present in a jitter measurement taken while no CD was playing, but while the receiver was still locked to the digital interface signal (fig21). These frequencies are due to factors not taken into account in software model: the first frequency can be accounted for by considering the change in the subframe preamble7; when a channel status block begins every 192 frames; it is possible that the 1.6kHz and 2.1kHz components are jitter artifacts inherent to the ADIC employed.

Finally, fig.22 shows the jitter noisefloor of the measurement system, obtained with the input of the ADC connected to ground (note the expanded amplitude scale in this diagram). The low level of jitter in this measurement indicates that the measurement system employed has not compromised the accuracy of the results obtained above. The good agreement achieved between practice and theory allows us to make predictions about the audibility of jitter errors in conversion electronics, based upon the band- limited interface jitter model developed above. An important result to note from the measurements is the high degree of correlation that can occur between audio and jitter signals. It is instructive to audition the PLL control voltage in an interface receiver after suitable amplification; the audio signal transmitted over the interface can be dearly heard (although it is noisy and highly distorted) as the PLL attempts to track jitter on the received interface signal (a Phenomenon also reported by van Willenswaard8).

The authors have found that track 2 of the Hi-Fi News & Record Review Test Disc 2 is particularly useful in this experiment, since it includes sections where identical signals are recorded in and out of phase across two stereo channels. The in-phase version is heard as a much louder signal at the PLL control voltage, since the PCM twos-complement-coded out- of-phase signal has a zero Zero-One sum across one interface frame. A clock used in an A/D or D/A conversion process that suffers from jitter that is highly correlated with the audio


7 AES3-1985, ibid.
8 Peter van Willenswaard, Stereophile, November 1990, Vol.13 No. 11, pp.78-83.

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e)

Fig20 Simulated interface jitter spectra for interface time constant of 65ns and a 1kHz audio signals at a) 0dBFS, b) -20dBFS, c) -40dBFS, and e)-80.65dBFS.


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