extremely low cutoff frequencies may be compromised in other performance aspects, such as initial lock-on time and the frequency range over which lock is maintained. These problems on be overcome by employing two PLLs in series, where the first has high bandwidth and fast startup, and the second low-bandwidth module is switched into circuit after conditions have stabilized.42 Low loop bandwidths can be achieved while maintaining wide lock range by using random access memory (RAM) to buffer the audio data before it is clocked out to the converter unit. A more fundamental solution to the problem of jitter is to locate a high-precision conversion clock inside the "receiver" (ie, DAC). This then creates the problem of how to match the transmitter and receiver data rates. One solution is to employ a RAM buffer for audio data where the rate at which the data is clocked out of the interface is under the control of the local clock.43 Enough memory must then be available to account for the long-term differences between the transmitted interface dock and the local oscillator frequencies. However, this is hardly an acceptable solution in a studio environment, where equipment must operate with identical sampling frequencies. A more general solution is to slave the receiver clock to the transmitter via a separate link, an approach adopted by Sony and Linn in their two-box CD systems. Details concerning how to implement the additional dock interface vary, but perhaps the most sensible and universal approach is to provide a second independent digital audio interface output at the receiver, from which the transmitter can derive a clock signal (fig.39). This scheme is also compatible with the recommendations made in AES11-1991.
Measuring
Jitter in the Digital Audio Interface: The simulations presented
above indicate that interface jitter may be a real problem in
practical audio systems. How can we measure the effects of such
jitter? In general, jitter errors in DACs will lie close to the
noisefloor of the conversion process, resulting in two basic problems
for measurement strategies:
42
Since this paper was presented in the fall of 1992, this practice
has become quite
widespread. --.JA
|
exercising the test system with full-scale audio signals, then errors in the ADC of a digital measurement system, also exalted to dose to full scale, may well swamp those due to jitter in the test device. Second, there is the problem of determining the source of measured errors. We have seen that jitter errors can contain both noise-like components and spectral lines, and that these can be confused with distortion and noise modulation due to DAC non-linearity. Noise-modulation tests in which the exciting audio frequency is chosen so that all DAC non-linearity falls on a limited number of FFT bins are perhaps the best-suited for revealing jitter errors. More work is required to develop a suitable test for jitter errors, although we can identify the tests currently in widespread use that will not reveal jitter errors. In the popular "fade-to-noise" test that measures level dependent logarithmic gain,44 ," the output of the test device is filtered with a 1/3-octave band-pass filter centered on the test frequency at lkHz - where jitter errors will not be detected, since no jitter error occurs at the fundamental frequency in either of the DAC error models discussed above. In the low-level noise modulation test where a 41Hz sinewave is applied to the device under test at levels of -40dB and below,45 the problems lie in signal levels that are too low to result in large jitter errors for either DAC model, and in a test frequency that will not excite large jitter errors in the 100% model. CONCLUSIONS Is the digital audio interface flawed? We have examined the possibilities of both amplitude and timing errors corrupting audio data transmitted across an interface. The probability of received amplitude errors is not high, and indeed they are most likely to occur in the preamble of each interface sub- frame. This me. am that if a receiver can lock onto an incoming interface signal, then the audio word values are safe. However, jitter remains a concern; jitter mechanisms exist for the biphase-mark encoded signal, the biggest problem being that of bandwidth limitation at an), stage of the interface. We have shown that band-limited interface jitter has a strong relationship to the bit structure of the serial interface code, and hence can be highly correlated with the transmitted audio data. Measurements have confirmed jitter levels of higher than 1ns in an above average interface circuit. The effects of jitter can be predicted by forming error models for different DAC architectures. It can be shown that, compared to low-oversampling multibit designs, pulse-density modulation converters are much more sensitive to jitter when producing low-frequency audio signals. This may explain certain subjective characteristics of PDM DACs that otherwise cannot be rationalized. A simple model of jitter-error audibility has shown that a DAC can tolerate white jitter noise of up to 180ps, but that even lower levels of sinusoidal jitter may be audible. These limits place tough constraints upon digital interface design, and it is recommended that interface receiver PLLs have closed-loop cutoff as low as possible. For the ultimate immunity to the effects of jitter, a second digital audio interface employed at the receiver can be used to slave the transmitter.
44
AES17-1991, "AES standard method for digital engineering -
Measurement of digital audio equipment," JAES,
December 1991, Vo139, pp.962 -975. |
to previous page Stereophile, March 1996 to first page |