|
19-0266; Rev 2a; 9/96
EVALUATION KIT
AVAILABLE High-Frequency Waveform Generator
MAX038
_______________General Description ____________________________Features
The MAX038 is a high-frequency, precision function o 0.1Hz to 20MHz Operating Frequency Range
generator producing accurate, high-frequency triangle,
sawtooth, sine, square, and pulse waveforms with a o Triangle, Sawtooth, Sine, Square, and Pulse
minimum of external components. The output frequency Waveforms
can be controlled over a frequency range of 0.1Hz to o Independent Frequency and Duty-Cycle
20MHz by an internal 2.5V bandgap voltage
reference and an external resistor and capacitor. The Adjustments
duty cycle can be varied over a wide range by applying o 350 to 1 Frequency Sweep Range
a ±2.3V control signal, facilitating pulse-width modula-
tion and the generation of sawtooth waveforms. o 15% to 85% Variable Duty Cycle
Frequency modulation and frequency sweeping are o Low-Impedance Output Buffer: 0.1
achieved in the same way. The duty cycle and
frequency controls are independent. o Low-Distortion Sine Wave: 0.75%
Sine, square, or triangle waveforms can be selected at o Low 200ppm/°C Temperature Drift
the output by setting the appropriate code at two
TTL-compatible select pins. The output signal for all ______________Ordering Information
waveforms is a 2VP-P signal that is symmetrical around PART TEMP. RANGE PIN-PACKAGE
ground. The low-impedance output can drive up
to ±20mA. MAX038CPP 0°C to +70°C 20 Plastic DIP
MAX038CWP 0°C to +70°C 20 SO
The TTL-compatible SYNC output from the internal
oscillator maintains a 50% duty cycle-regardless of MAX038C/D 0°C to +70°C Dice*
the duty cycle of the other waveforms-to synchronize MAX038EPP -40°C to +85°C 20 Plastic DIP
other devices in the system. The internal oscillator can MAX038EWP -40°C to +85°C 20 SO
be synchronized to an external TTL clock connected
to PDI. *Contact factory for dice specifications.
________________________Applications __________________Pin Configuration
Precision Function Generators
Voltage-Controlled Oscillators
Frequency Modulators TOP VIEW
Pulse-Width Modulators REF 1 20 V-
Phase-Locked Loops GND 2 19 OUT
Frequency Synthesizer A0 3 18 GND
FSK Generator-Sine and Square Waves A1 4 MAX038 17 V+
COSC 5 16 DV+
GND 6 15 DGND
DADJ 7 14 SYNC
FADJ 8 13 PDI
GND 9 12 PDO
IIN 10 11 GND
DIP/SO
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
High-Frequency Waveform Generator
ABSOLUTE MAXIMUM RATINGS
V+ to GND ................................................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C)
DV+ to DGND...........................................................-0.3V to +6V Plastic DIP (derate 11.11mW/°C above +70°C) ..........889mW
V- to GND .................................................................+0.3V to -6V SO (derate 10.00mW/°C above +70°C).......................800mW
Pin Voltages CERDIP (derate 11.11mW/°C above +70°C)...............889mW
IIN, FADJ, DADJ, PDO .....................(V- - 0.3V) to (V+ + 0.3V) Operating Temperature Ranges
COSC .....................................................................+0.3V to V- MAX038C_ _ .......................................................0°C to +70°C
MAX038 A0, A1, PDI, SYNC, REF.........................................-0.3V to V+ MAX038E_ _ ....................................................-40°C to +85°C
GND to DGND ................................................................±0.3V Maximum Junction Temperature .....................................+150°C
Maximum Current into Any Pin .........................................±50mA Storage Temperature Range .............................-65°C to +150°C
OUT, REF Short-Circuit Duration to GND, V+, V- ...............30sec Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, GND = DGND = 0V, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, CF = 100pF,
RIN = 25k , RL = 1k , CL = 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FREQUENCY CHARACTERISTICS
Maximum Operating Frequency Fo 15pCF 15pF, IIN = 500µA 20.0 40.0 MHz
Frequency Programming VFADJ = 0V 2.50 750
Current IIN µA
VFADJ = -3V 1.25 375
IIN Offset Voltage VIN ±1.0 ±2.0 mV
Frequency Temperature Fo/°C VFADJ = 0V 600
Coefficient ppm/°C
Fo/°C VFADJ = -3V 200
( Fo/Fo)
V+ V- = -5V, V+ = 4.75V to 5.25V ±0.4 ±2.00
Frequency Power-Supply
Rejection ( F %/V
o/Fo)
V- V+ = 5V, V- = -4.75V to -5.25V ±0.2 ±1.00
OUTPUT AMPLIFIER (applies to all waveforms)
Output Peak-to-Peak Symmetry VOUT ±4 mV
Output Resistance ROUT 0.1 0.2
Output Short-Circuit Current IOUT Short circuit to GND 40 mA
SQUARE-WAVE OUTPUT (RL = 100 )
Amplitude VOUT 1.9 2.0 2.1 VP-P
Rise Time tR 10% to 90% 12 ns
Fall Time tF 90% to 10% 12 ns
Duty Cycle dc VDADJ = 0V, dc = tON/t x 100% 47 50 53 %
TRIANGLE-WAVE OUTPUT (RL = 100 )
Amplitude VOUT 1.9 2.0 2.1 VP-P
Nonlinearity Fo = 100kHz, 5% to 95% 0.5 %
Duty Cycle dc VDADJ = 0V (Note 1) 47 50 53 %
SINE-WAVE OUTPUT (RL = 100 )
Amplitude VOUT 1.9 2.0 2.1 VP-P
Duty cycle adjusted to 50% 0.75
Total Harmonic Distortion THD %
Duty cycle unadjusted 1.50
2 _______________________________________________________________________________________
High-Frequency Waveform Generator
MAX038
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, GND = DGND = 0V, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, CF = 100pF,
RIN = 25k , RL = 1k , CL = 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SYNC OUTPUT
Output Low Voltage VOL ISINK = 3.2mA 0.3 0.4 V
Output High Voltage VOH ISOURCE = 400µA 2.8 3.5 V
Rise Time tR 10% to 90%, RL = 3k , CL = 15pF 10 ns
Fall Time tF 90% to 10%, RL = 3k , CL = 15pF 10 ns
Duty Cycle dcSYNC 50 %
DUTY-CYCLE ADJUSTMENT (DADJ)
DADJ Input Current IDADJ 190 250 320 µA
DADJ Voltage Range VDADJ ±2.3 V
Duty-Cycle Adjustment Range dc -2.3V VDADJ 2.3V 15 85 %
DADJ Nonlinearity dc/VFADJ -2V VDADJ 2V 2 4 %
Change in Output Frequency
with DADJ Fo/VDADJ -2V VDADJ 2V ±2.5 ±8 %
Maximum DADJ Modulating
Frequency FDC 2 MHz
FREQUENCY ADJUSTMENT (FADJ)
FADJ Input Current IFADJ 190 250 320 µA
FADJ Voltage Range VFADJ ±2.4 V
Frequency Sweep Range Fo -2.4V VFADJ 2.4V ±70 %
FM Nonlinearity with FADJ Fo/VFADJ -2V VFADJ 2V ±0.2 %
Change in Duty Cycle with FADJ dc/VFADJ -2V VFADJ 2V ±2 %
Maximum FADJ Modulating
Frequency FF 2 MHz
VOLTAGE REFERENCE
Output Voltage VREF IREF = 0 2.48 2.50 2.52 V
Temperature Coefficient VREF/°C 20 ppm/°C
0mA IREF 4mA (source) 1 2
Load Regulation VREF/IREF -100µA IREF 0µA (sink) 1 4 mV/mA
Line Regulation VREF/V+ 4.75V V+ 5.25V (Note 2) 1 2 mV/V
LOGIC INPUTS (A0, A1, PDI)
Input Low Voltage VIL 0.8 V
Input High Voltage VIH 2.4 V
Input Current (A0, A1) IIL, IIH VA0, VA1 = VIL, VIH ±5 µA
Input Current (PDI) IIL, IIH VPDI = VIL, VIH ±25 µA
POWER SUPPLY
Positive Supply Voltage V+ 4.75 5.25 V
SYNC Supply Voltage DV+ 4.75 5.25 V
Negative Supply Voltage V- -4.75 -5.25 V
Positive Supply Current I+ 35 45 mA
SYNC Supply Current IDV+ 1 2 mA
Negative Supply Current I- 45 55 mA
Note 1: Guaranteed by duty-cycle test on square wave.
Note 2: VREF is independent of V-.
_______________________________________________________________________________________ 3
High-Frequency Waveform Generator
__________________________________________Typical Operating Characteristics
(Circuit of Figure 1, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, RL = 1k , CL = 20pF, TA = +25°C, unless
otherwise noted.)
OUTPUT FREQUENCY NORMALIZED OUTPUT FREQUENCY
vs. IIN CURRENT vs. FADJ VOLTAGE
MAX038 100M 2.0
1.8 IIN = 100µA, COSC = 1000pF
MAX038-08 33pF MAX038-09
10M 1.6
100pF 1.4
330pF 1.2
1M 1.0
3.3nF NORMALIZED 0.8
100k F OUT 0.6
33nF 0.4
10k 100nF 0.2
0
-3 -2 -1 0 1 2 3
OUTPUT FREQUENCY (Hz) 1k 1µF VFADJ (V)
3.3µF
100 DUTY CYCLE vs. DADJ VOLTAGE
10µF 100
47µF 90
10 MAX038-16B
100µF 80
70
1 60
50
0.1 40
1 10 100 1000 DUTY CYCLE (%) 30
IIN CURRENT (µA) 20
10 IIN = 200µA
0
-3 -2 -1 0 1 2 3
DADJ (V)
NORMALIZED OUTPUT FREQUENCY DUTY-CYCLE LINEARITY
vs. DADJ VOLTAGE vs. DADJ VOLTAGE
1.10 2.0
I I
IN = 10µA IN = 500µA
MAX038-17 1.5 MAX038-18
1.05 IIN = 25µA 1.0
IIN = 50µA 0.5 I
1.00 IN = 250µA
0
I
-0.5 IN = 100µA
0.95 IIN = 100µA -1.0
IIN = 250µA
0.90 -1.5 IIN = 50µA
NORMALIZED OUTPUT FREQUENCY IIN = 500µA DUTY-CYCLE LINEARITY ERROR (%) -2.0 IIN = 25µA
I
0.85 -2.5 IN = 10µA
-2.0 -1.0 0 1.0 1.5 2.5
DADJ (V) DADJ (V)
4 _______________________________________________________________________________________
High-Frequency Waveform Generator
MAX038
____________________________Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, RL = 1k , CL = 20pF, TA = +25°C, unless
otherwise noted.)
SINE-WAVE OUTPUT (50Hz) SINE-WAVE OUTPUT (20MHz)
TOP: OUTPUT 50Hz = Fo IIN = 400µA
BOTTOM: SYNC CF = 20pF
IIN = 50µA
CF = 1µF TRIANGLE-WAVE OUTPUT (50Hz) TRIANGLE-WAVE OUTPUT (20MHz)
TOP: OUTPUT 50Hz = Fo IIN = 400µA
BOTTOM: SYNC CF = 20pF
IIN = 50µA
CF = 1µF SQUARE-WAVE OUTPUT (50Hz)
TOP: OUTPUT 50Hz = Fo
BOTTOM: SYNC
IIN = 50µA
CF = 1µF
_______________________________________________________________________________________ 5
High-Frequency Waveform Generator
____________________________Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, RL = 1k , CL = 20pF, TA = +25°C, unless
otherwise noted.)
SQUARE-WAVE OUTPUT (20MHz) FREQUENCY MODULATION USING FADJ
MAX038
0.5V
0
-0.5V
IIN = 400µA TOP: OUTPUT
CF = 20pF BOTTOM: FADJ
FREQUENCY MODULATION USING IIN FREQUENCY MODULATION USING IIN
TOP: OUTPUT TOP: OUTPUT
BOTTOM: IIN BOTTOM: IIN
PULSE-WIDTH MODULATION USING DADJ
+1V
0V
-1V
+2V
0V
-2V
TOP: SQUARE-WAVE OUT, 2VP-P
BOTTOM: VDADJ, -2V to +2.3V
6 _______________________________________________________________________________________
High-Frequency Waveform Generator
MAX038
____________________________Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, RL = 1k , CL = 20pF, TA = +25°C, unless
otherwise noted.)
OUTPUT SPECTRUM, SINE WAVE OUTPUT SPECTRUM, SINE WAVE
(Fo = 11.5MHz) (Fo = 5.9kHz)
0 0
RIN = 15k (VIN = 2.5V), CF = 20pF, 12B
RIN = 51k (VIN = 2.5V), CF = 0.01µF,
-10 VDADJ = 40mV, VFADJ = -3V -10 V
MAX038-12A DADJ = 50mV, VFADJ = 0V MAX038
-20 -20
-30 -30
-40 -40
-50 -50
-60 -60
ATTENUATION (dB) -70 ATTENUATION (dB) -70
-80 -80
-90 -90
-100 -100
0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50
FREQUENCY (MHz) FREQUENCY (kHz)
______________________________________________________________Pin Description
PIN NAME FUNCTION
1 REF 2.50V bandgap voltage reference output
2, 6, 9, GND Ground*
11, 18
3 A0 Waveform selection input; TTL/CMOS compatible
4 A1 Waveform selection input; TTL/CMOS compatible
5 COSC External capacitor connection
7 DADJ Duty-cycle adjust input
8 FADJ Frequency adjust input
10 IIN Current input for frequency control
12 PDO Phase detector output. Connect to GND if phase detector is not used.
13 PDI Phase detector reference clock input. Connect to GND if phase detector is not used.
TTL/CMOS-compatible output, referenced between DGND and DV+. Permits the internal oscillator to be
14 SYNC synchronized with an external signal. Leave open if unused.
15 DGND Digital ground
16 DV+ Digital +5V supply input. Can be left open if SYNC is not used.
17 V+ +5V supply input
19 OUT Sine, square, or triangle output
20 V- -5V supply input
*The five GND pins are not internally connected. Connect all five GND pins to a quiet ground close to the device. A ground plane is
recommended (see Layout Considerations).
_______________________________________________________________________________________ 7
High-Frequency Waveform Generator
3 4
A0 A1
5 COSC TRIANGLE
SINE
OSCILLATOR OSC A SINE
CF 6 GND OSC B SHAPER
MAX038 TRIANGLE OUT 19
MUX
SQUARE
8 FADJ R
OSCILLATOR L CL
7 CURRENT COMPARATOR
DADJ GENERATOR
10 IIN
MAX038
RF RD RIN -250µA
SYNC 14
COMPARATOR
1 REF 2.5V
VOLTAGE
REFERENCE
* 17 V+ PDO 12
+5V PHASE
20 V-
-5V DETECTOR PDI 13
2, 9, 11, 18 GND
DGND DV+
15 16
*
= SIGNAL DIRECTION, NOT POLARITY +5V
= BYPASS CAPACITORS ARE 1µF CERAMIC OR 1µF ELECTROLYTIC IN PARALLEL WITH 1nF CERAMIC.
*
Figure 1. Block Diagram and Basic Operating Circuit
_______________Detailed Description with constant currents, simultaneously producing a tri-
The MAX038 is a high-frequency function generator angle wave and a square wave (Figure 1). The charg-
that produces low-distortion sine, triangle, sawtooth, or ing and discharging currents are controlled by the cur-
square (pulse) waveforms at frequencies from less than rent flowing into IIN, and are modulated by the voltages
1Hz to 20MHz or more, using a minimum of external applied to FADJ and DADJ. The current into IIN can be
components. Frequency and duty cycle can be inde- varied from 2µA to 750µA, producing more than two
pendently controlled by programming the current, volt- decades of frequency for any value of CF. Applying
age, or resistance. The desired output waveform is ±2.4V to FADJ changes the nominal frequency (with
selected under logic control by setting the appropriate VFADJ = 0V) by ±70%; this procedure can be used for
code at the A0 and A1 inputs. A SYNC output and fine control.
phase detector are included to simplify designs requir- Duty cycle (the percentage of time that the output wave-
ing tracking to an external signal source. form is positive) can be controlled from 10% to 90% by
The MAX038 operates with ±5V ±5% power supplies. applying ±2.3V to DADJ. This voltage changes the CF
The basic oscillator is a relaxation type that operates by charging and discharging current ratio while maintaining
alternately charging and discharging a capacitor, C nearly constant frequency.
F,
8 _______________________________________________________________________________________
High-Frequency Waveform Generator
MAX038
A stable 2.5V reference voltage, REF, allows simple VFADJ = 0V, the fundamental output frequency (Fo) is
determination of IIN, FADJ, or DADJ with fixed resistors, given by the formula:
and permits adjustable operation when potentiometers F
are connected from each of these inputs to REF. FADJ o (MHz) = IIN (µA) ÷ CF (pF) [1]
and/or DADJ can be grounded, producing the nominal The period (to) is:
frequency with a 50% duty cycle. to (µs) = CF (pF) ÷ IIN (µA) [2]
The output frequency is inversely proportional to where:
capacitor CF. CF values can be selected to produce I
frequencies above 20MHz. IN = current injected into IIN (between 2µA and
750µA)
A sine-shaping circuit converts the oscillator triangle C
wave into a low-distortion sine wave with constant F = capacitance connected to COSC and GND
(20pF to >100µF).
amplitude. The triangle, square, and sine waves are
input to a multiplexer. Two address lines, A0 and A1, For example:
control which of the three waveforms is selected. The 0.5MHz = 100µA ÷ 200pF
output amplifier produces a constant 2VP-P amplitude and
(±1V), regardless of wave shape or frequency. 2µs = 200pF ÷ 100µA
The triangle wave is also sent to a comparator that pro-
duces a high-speed square-wave SYNC waveform that Optimum performance is achieved with IIN between
can be used to synchronize other oscillators. The SYNC 10µA and 400µA, although linearity is good with IIN
circuit has separate power-supply leads and can be between 2µA and 750µA. Current levels outside of this
disabled. range are not recommended. For fixed-frequency oper-
ation, set I
Two other phase-quadrature square waves are gener- IN to approximately 100µA and select a suit-
able capacitor value. This current produces the lowest
ated in the basic oscillator and sent to one side of an temperature coefficient, and produces the lowest fre-
"exclusive-OR" phase detector. The other side of the quency shift when varying the duty cycle.
phase-detector input (PDI) can be connected to an
external oscillator. The phase-detector output (PDO) is The capacitance can range from 20pF to more than
a current source that can be connected directly to 100µF, but stray circuit capacitance must be minimized
FADJ to synchronize the MAX038 with the external by using short traces. Surround the COSC pin and the
oscillator. trace leading to it with a ground plane to minimize cou-
pling of extraneous signals to this node. Oscillation
Waveform Selection above 20MHz is possible, but waveform distortion
The MAX038 can produce either sine, square, or trian- increases under these conditions. The low frequency
gle waveforms. The TTL/CMOS-logic address pins (A0 limit is set by the leakage of the COSC capacitor and
and A1) set the waveform, as shown below: by the required accuracy of the output frequency.
Lowest frequency operation with good accuracy is usu-
A0 A1 WAVEFORM ally achieved with 10µF or greater non-polarized
X 1 Sine wave capacitors.
0 0 Square wave An internal closed-loop amplifier forces IIN to virtual
1 0 Triangle wave ground, with an input offset voltage less than ±2mV. IIN
may be driven with either a current source (IIN), or a
X = Don't care voltage (VIN) in series with a resistor (RIN). (A resistor
Waveform switching can be done at any time, without between REF and IIN provides a convenient method of
regard to the phase of the output. Switching occurs generating IIN: IIN = VREF/RIN.) When using a voltage
within 0.3µs, but there may be a small transient in the in series with a resistor, the formula for the oscillator fre-
output waveform that lasts 0.5µs. quency is:
F
Waveform Timing o (MHz) = VIN ÷ [RIN x CF (pF)] [3]
and:
Output Frequency
The output frequency is determined by the current to (µs) = CF (pF) x RIN ÷ VIN [4]
injected into the IIN pin, the COSC capacitance (to
ground), and the voltage on the FADJ pin. When
_______________________________________________________________________________________ 9
High-Frequency Waveform Generator
When the MAX038's frequency is controlled by a volt- to = period when VFADJ = 0V.
age source (VIN) in series with a fixed resistor (RIN), the Conversely, if V
output frequency is a direct function of V FADJ is known, the frequency is given
IN as shown in by:
the above equations. Varying VIN modulates the oscilla-
tor frequency. For example, using a 10k resistor for Fx = Fo x (1 - [0.2915 x VFADJ]) [8]
RIN and sweeping VIN from 20mV to 7.5V produces and the period (tx) is:
large frequency deviations (up to 375:1). Select R
MAX038 IN so t
that I x = to ÷ (1 - [0.2915 x VFADJ]) [9]
IN stays within the 2µA to 750µA range. The band-
width of the IIN control amplifier, which limits the modu- Programming FADJ
lating signal's highest frequency, is typically 2MHz. FADJ has a 250µA constant current sink to V- that must
IIN can be used as a summing point to add or subtract be furnished by the voltage source. The source is usu-
currents from several sources. This allows the output ally an op-amp output, and the temperature coefficient
frequency to be a function of the sum of several vari- of the current sink becomes unimportant. For manual
ables. As VIN approaches 0V, the IIN error increases adjustment of the deviation, a variable resistor can be
due to the offset voltage of IIN. used to set VFADJ, but then the 250µA current sink's
temperature coefficient becomes significant. Since
Output frequency will be offset 1% from its final value external resistors cannot match the internal tempera-
for 10 seconds after power-up. ture-coefficient curve, using external resistors to pro-
FADJ Input gram VFADJ is intended only for manual operation,
The output frequency can be modulated by FADJ, when the operator can correct for any errors. This
which is intended principally for fine frequency control, restriction does not apply when VFADJ is a true voltage
usually inside phase-locked loops. Once the funda- source.
mental, or center frequency (Fo) is set by IIN, it may be A variable resistor, RF, connected between REF (+2.5V)
changed further by setting FADJ to a voltage other than and FADJ provides a convenient means of manually
0V. This voltage can vary from -2.4V to +2.4V, causing setting the frequency deviation. The resistance value
the output frequency to vary from 1.7 to 0.30 times the (RF) is:
value when FADJ is 0V (Fo ±70%). Voltages beyond R
±2.4V can cause instability or cause the frequency F = (VREF - VFADJ) ÷ 250µA [10]
change to reverse slope. VREF and VFADJ are signed numbers, so use correct
algebraic convention. For example, if V
The voltage on FADJ required to cause the output to FADJ is -2.0V
(+58.3% deviation), the formula becomes:
deviate from Fo by Dx (expressed in %) is given by the
formula: RF = (+2.5V - (-2.0V)) ÷ 250µA
VFADJ = -0.0343 x Dx [5] = (4.5V) ÷ 250µA
where VFADJ, the voltage on FADJ, is between = 18k
-2.4V and +2.4V. Disabling FADJ
Note: While IIN is directly proportional to the fundamen- The FADJ circuit adds a small temperature coefficient
tal, or center frequency (Fo), VFADJ is linearly related to to the output frequency. For critical open-loop applica-
% deviation from Fo. VFADJ goes to either side of 0V, tions, it can be turned off by connecting FADJ to GND
corresponding to plus and minus deviation. (not REF) through a 12k resistor (R1 in Figure 2). The
The voltage on FADJ for any frequency is given by the -250µA current sink at FADJ causes -3V to be devel-
formula: oped across this resistor, producing two results. First,
the FADJ circuit remains in its linear region, but discon-
VFADJ = (Fo - Fx) ÷ (0.2915 x Fo) [6] nects itself from the main oscillator, improving tempera-
where: ture stability. Second, the oscillator frequency doubles.
Fx = output frequency If FADJ is turned off in this manner, be sure to correct
equations 1-4 and 6-9 above, and 12 and 14 below by
Fo = frequency when VFADJ = 0V. doubling Fo or halving to. Although this method doubles
Likewise, for period calculations: the normal output frequency, it does not double the
VFADJ = 3.43 x (tx - to) ÷ tx [7] upper frequency limit. Do not operate FADJ open cir-
cuit or with voltages more negative than -3.5V. Doing
where: so may cause transistor saturation inside the IC, lead-
tx = output period ing to unwanted changes in frequency and duty cycle.
10 ______________________________________________________________________________________
High-Frequency Waveform Generator
MAX038
5V +5V PRECISION DUTY-CYCLE ADJUSTMENT CIRCUIT
R4 R3
20 17 4 2.5V +2.5V
FREQUENCY 100k 100k
1 V- C2
REF V+ A1 3 1µF REF
C1 C3 AO
1µF 1nF
RIN 7 DADJ MAX038
20k R2 MAX038
50
10 19
IIN OUT SINE-WAVE
8 OUTPUT R7 R5
FADJ 100k 100k
16
R1 DV+ N.C.
15
12k DGND R6
14 5k
SYNC N.C.
13
PDI
5 12 2 x 2.5V
COSC PDO Fo = R DADJ
IN x CF
GND GND GND GND GND
CF 6 2 9 11 18
ADJUST R6 FOR MINIMUM SINE-WAVE DISTORTION
Figure 2. Operating Circuit with Sine-Wave Output and 50% Duty Cycle; SYNC and FADJ Disabled
With FADJ disabled, the output frequency can still be DADJ can be used to reduce the sine-wave distortion.
changed by modulating IIN. The unadjusted duty cycle (VDADJ = 0V) is 50% ±2%;
any deviation from exactly 50% causes even order har-
Swept Frequency Operation monics to be generated. By applying a small
The output frequency can be swept by applying a vary- adjustable voltage (typically less than ±100mV) to
ing signal to IIN or FADJ. IIN has a wider range, slightly VDADJ, exact symmetry can be attained and the distor-
slower response, lower temperature coefficient, and tion can be minimized (see Figure 2).
requires a single polarity current source. FADJ may be
used when the swept range is less than ±70% of the The voltage on DADJ needed to produce a specific
center frequency, and it is suitable for phase-locked duty cycle is given by the formula:
loops and other low-deviation, high-accuracy closed- VDADJ = (50% - dc) x 0.0575 [11]
loop controls. It uses a sweeping voltage symmetrical or:
about ground. V
Connecting a resistive network between REF, the volt- DADJ = (0.5 - [tON ÷ to]) x 5.75 [12]
age source, and FADJ or IIN is a convenient means of where:
offsetting the sweep voltage. VDADJ = DADJ voltage (observe the polarity)
Duty Cycle dc = duty cycle (in %)
The voltage on DADJ controls the waveform duty cycle tON = ON (positive) time
(defined as the percentage of time that the output to = waveform period.
waveform is positive). Normally, VDADJ = 0V, and the
duty cycle is 50% (Figure 2). Varying this voltage from Conversely, if VDADJ is known, the duty cycle and ON
+2.3V to -2.3V causes the output duty cycle to vary time are given by:
from 15% to 85%, about -15% per volt. Voltages dc = 50% - (VDADJ x 17.4) [13]
beyond ±2.3V can shift the output frequency and/or tON = to x (0.5 - [VDADJ x 0.174]) [14]
cause instability.
______________________________________________________________________________________ 11
High-Frequency Waveform Generator
Programming DADJ for low temperature coefficient over the whole tempera-
DADJ is similar to FADJ; it has a 250µA constant cur- ture range. NPO ceramics are usually satisfactory.
rent sink to V- that must be furnished by the voltage The voltage on COSC is a triangle wave that varies
source. The source is usually an op-amp output, and between 0V and -1V. Polarized capacitors are generally
the temperature coefficient of the current sink becomes not recommended (because of their outrageous tem-
unimportant. For manual adjustment of the duty cycle, a perature dependence and leakage currents), but if they
variable resistor can be used to set V
MAX038 DADJ, but then the are used, the negative terminal should be connected to
250µA current sink's temperature coefficient becomes COSC and the positive terminal to GND. Large-value
significant. Since external resistors cannot match the capacitors, necessary for very low frequencies, should
internal temperature-coefficient curve, using external be chosen with care, since potentially large leakage
resistors to program VDADJ is intended only for manual currents and high dielectric absorption can interfere
operation, when the operator can correct for any errors. with the orderly charge and discharge of C
This restriction does not apply when V F. If possi-
DADJ is a true ble, for a given frequency, use lower IIN currents to
voltage source. reduce the size of the capacitor.
A variable resistor, RD, connected between REF
(+2.5V) and DADJ provides a convenient means of SYNC Output
manually setting the duty cycle. The resistance value SYNC is a TTL/CMOS-compatible output that can be
(RD) is: used to synchronize external circuits. The SYNC output
is a square wave whose rising edge coincides with the
RD = (VREF - VDADJ) ÷ 250µA [15] output rising sine or triangle wave as it crosses through
Note that both VREF and VDADJ are signed values, so 0V. When the square wave is selected, the rising edge
observe correct algebraic convention. For example, if of SYNC occurs in the middle of the positive half of the
VDADJ is -1.5V (23% duty cycle), the formula becomes: output square wave, effectively 90° ahead of the output.
RD = (+2.5V - (-1.5V)) ÷ 250µA The SYNC duty cycle is fixed at 50% and is indepen-
dent of the DADJ control.
= (4.0V) ÷ 250µA = 16k Because SYNC is a very-high-speed TTL output, the
Varying the duty cycle in the range 15% to 85% has high-speed transient currents in DGND and DV+ can
minimal effect on the output frequency-typically less radiate energy into the output circuit, causing a narrow
than 2% when 25µA < IIN < 250µA. The DADJ circuit is spike in the output waveform. (This spike is difficult to
wideband, and can be modulated at up to 2MHz (see see with oscilloscopes having less than 100MHz band-
photos, Typical Operating Characteristics). width). The inductance and capacitance of IC sockets
Output tend to amplify this effect, so sockets are not recom-
The output amplitude is fixed at 2VP-P, symmetrical mended when SYNC is on. SYNC is powered from sep-
around ground, for all output waveforms. OUT has an arate ground and supply pins (DGND and DV+), and it
output resistance of under 0.1 , and can drive ±20mA can be turned off by making DV+ open circuit. If syn-
with up to a 50pF load. Isolate higher output capaci- chronization of external circuits is not used, turning off
tance from OUT with a resistor (typically 50 ) or buffer SYNC by DV+ opening eliminates the spike.
amplifier. Phase Detectors
Reference Voltage Internal Phase Detector
REF is a stable 2.50V bandgap voltage reference capa- The MAX038 contains a TTL/CMOS phase detector that
ble of sourcing 4mA or sinking 100µA. It is principally can be used in a phase-locked loop (PLL) to synchro-
used to furnish a stable current to IIN or to bias DADJ nize its output to an external signal (Figure 3). The
and FADJ. It can also be used for other applications external source is connected to the phase-detector
external to the MAX038. Bypass REF with 100nF to min- input (PDI) and the phase-detector output is taken from
imize noise. PDO. PDO is the output of an exclusive-OR gate, and
produces a rectangular current waveform at the
Selecting Resistors and Capacitors MAX038 output frequency, even with PDI grounded.
The MAX038 produces a stable output frequency over PDO is normally connected to FADJ and a resistor,
time and temperature, but the capacitor and resistors R
that determine frequency can degrade performance if PD, and a capacitor CPD, to GND. RPD sets the gain
of the phase detector, while the capacitor attenuates
they are not carefully chosen. Resistors should be high-frequency components and forms a pole in the
metal film, 1% or better. Capacitors should be chosen phase-locked loop filter.
12 ______________________________________________________________________________________
High-Frequency Waveform Generator
MAX038
charge CPD, so the rate at which VFADJ changes (the
+5V -5V C1
1µF loop bandwidth) is inversely proportional to CPD.
C2 The phase error (deviation from phase quadrature)
1µF depends on the open-loop gain of the PLL and the ini-
14 16 17 20 4
CENTER tial frequency deviation of the oscillator from the exter-
FREQUENCY SYNC DV+ V+ V- A1
1 3 nal signal source. The oscillator conversion gain (Ko) is:
REF A0 KO = o ÷ VFADJ [17]
RD 7 DADJ ROUT which, from equation [6] is:
50
10 19 KO = 3.43 x o (radians/sec) [18]
IIN OUT
8 MAX038 RF
FADJ The loop gain of the PLL system (KV) is:
OUTPUT
R KV = KD x KO [19]
PD
13 where:
PDI
5 12 K
COSC D = detector gain
PDO
CPD CF
GND GND GND GND GND DGND KO = oscillator gain.
2 6 9 11 18 15 With a loop filter having a response F(s), the open-loop
transfer function, T(s), is:
T(s) = KD x KO x F(s) ÷ s [20]
EXTERNAL OSC INPUT Using linear feedback analysis techniques, the closed-
loop transfer characteristic, H(s), can be related to the
open-loop transfer function as follows:
Figure 3. Phase-Locked Loop Using Internal Phase Detector H(s) = T(s) ÷ [1+ T(s)] [21]
The transient performance and the frequency response
PDO is a rectangular current-pulse train, alternating of the PLL depends on the choice of the filter charac-
between 0µA and 500µA. It has a 50% duty cycle when teristic, F(s).
the MAX038 output and PDI are in phase-quadrature When the MAX038 internal phase detector is not used,
(90° out of phase). The duty cycle approaches 100% PDI and PDO should be connected to GND.
as the phase difference approaches 180° and con-
versely, approaches 0% as the phase difference External Phase Detectors
approaches 0°. The gain of the phase detector (KD) External phase detectors may be used instead of the
can be expressed as: internal phase detector. The external phase detector
K shown in Figure 4 duplicates the action of the MAX038's
D = 0.318 x RPD (volts/radian) [16] internal phase detector, but the optional ÷N circuit can
where RPD = phase-detector gain-setting resistor. be placed between the SYNC output and the phase
When the loop is in lock, the input signals to the phase detector in applications requiring synchronizing to an
detector are in approximate phase quadrature, the duty exact multiple of the external oscillator. The resistor net-
cycle is 50%, and the average current at PDO is 250µA work consisting of R4, R5, and R6 sets the sync range,
(the current sink of FADJ). This current is divided while capacitor C4 sets the capture range. Note that
between FADJ and RPD; 250µA always goes into FADJ this type of phase detector (with or without the ÷N cir-
and any difference current is developed across RPD, cuit) locks onto harmonics of the external oscillator as
creating VFADJ (both polarities). For example, as the well as the fundamental. With no external oscillator
phase difference increases, PDO duty cycle increases, input, this circuit can be unpredictable, depending on
the average current increases, and the voltage on RPD the state of the external input DC level.
(and VFADJ) becomes more positive. This in turn Figure 4 shows a frequency phase detector that locks
decreases the oscillator frequency, reducing the phase onto only the fundamental of the external oscillator.
difference, thus maintaining phase lock. The higher With no external oscillator input, the output of the fre-
RPD is, the greater VFADJ is for a given phase differ- quency phase detector is a positive DC voltage, and
ence; in other words, the greater the loop gain, the less the oscillations are at the lowest frequency as set by
the capture range. The current from PDO must also R4, R5, and R6.
______________________________________________________________________________________ 13
High-Frequency Waveform Generator
+5V -5V C1
1µF
C2
1µF
÷N
14 16 17 20 4
CENTER
MAX038 SYNC DV+ V+ V- A1
FREQUENCY 1 3
REF A0
R2
CW
R3 7 DADJ MAX038 R1
50
PHASE DETECTOR 10 19
R4 IIN OUT RF
8 OUTPUT
FADJ
R5 R6 13
OFFSET GAIN
EXTERNAL PDI
5 12
OSC INPUT COSC PDO
-5V
GND GND GND GND GND DGND
C4 C3 2 6 9 11 18 15
CAPTURE FREQUENCY
Figure 4. Phase-Locked Loop Using External Phase Detector
+5V -5V C1
1µF
C2
1µF
÷N
14 16 17 20 4
CENTER SYNC DV+ V+ V- A1
FREQUENCY 1 3
REF A0
R2
CW
R3 7
FREQUENCY PHASE DETECTOR DADJ MAX038 R1
50
10 19
R4 IIN OUT
8 FADJ RF
OUTPUT
R5 R6
EXTERNAL 13
OFFSET GAIN
OSC INPUT PDI
5 12
COSC PDO
-5V
GND GND GND GND GND DGND
C4 C3 2 6 9 11 18 15
CAPTURE FREQUENCY
Figure 5. Phase-Locked Loop Using External Frequency Phase Detector
14 ______________________________________________________________________________________
High-Frequency Waveform Generator
MAX038
SIGNAL OUTPUT SYNC OUTPUT
56pF
+5V 50 -5V
220nH 110pF
, 50MHz 50 LOWPASS FILTER
220nH 56pF
50.0 100
µF0.1 FREQUENCY SYNTHESIZER 1kHz RESOLUTION; 8kHz TO 16.383MHz
µF0.1
0.1 µF
20 11
V- OUT V+
GND DV+ PDI
DGND SYNC PDO GND1
µA
1N914 2µA to 750
MAX038
2N3906
1k VREF GND1 A0 A1 COSC GND1 DADJ FADJ GND1 IIN
7 1 10
WAVEFORM SELECT
8 4 35 pF
MAX412
6 5 2.7M
1k
1 3.33k +2.5V ±2.5V
2N3904 µF0.1
MAX412
3 2 0V TO 2.5V 10k
µF µF
7.5k
0.1 0.1
1 18
OUT1 RFB µF 6
0.1
OUT2 VREF 7 4
GND VDD
MX7541 MAX427
BIT1 BIT12 2 3 µF
33k
BIT2 BIT11 33k 0.1
BIT3 BIT10
BIT4 BIT9 3.3M 3.3M µF
BIT5 BIT8 0.1
BIT6 BIT7
9 10 PDV PDR
14 1
1kHz N3 N2 N1 N0 FV
2kHz PDV PDR RA2 RA1 RA0 OUT V DD V SS F IN
PD1
4kHz
8kHz
16kHz MC145151 OUT IN
32kHz
N4 N5 NN6 N7 N8 N9 T/R N12 N13 N10 N11 OSC OSC LD
64kHz 15
128kHz 28
256kHz
512kHz 8.192MHz
1.024MHz
2.048MHz 35pF
4.096MHz 20pF
8.192MHz
Figure 6. Crystal-Controlled, Digitally Programmed Frequency Synthesizer-8kHz to 16MHz with 1kHz Resolution
______________________________________________________________________________________ 15
High-Frequency Waveform Generator
Layout Considerations tor compares the ÷N output with the MAX038 SYNC
Realizing the full performance of the MAX038 requires output and sends differential phase information to U5.
careful attention to power-supply bypassing and board U5's single-ended output is summed with an offset into
layout. Use a low-impedance ground plane, and con- the FADJ input. (Using the DAC and the IIN pin for
nect all five GND pins directly to it. Bypass V+ and V- coarse frequency control allows the FADJ pin to have
directly to the ground plane with 1µF ceramic capaci- very fine control with reasonably fast response to switch
changes.)
MAX038 tors or 1µF tantalum capacitors in parallel with 1nF
ceramics. Keep capacitor leads short (especially with A 50MHz, 50 lowpass filter in the output allows pas-
the 1nF ceramics) to minimize series inductance. sage of 16MHz square waves and triangle waves with
If SYNC is used, DV+ must be connected to V+, DGND reasonable fidelity, while stopping high-frequency noise
must be connected to the ground plane, and a second generated by the ÷N circuit.
1nF ceramic should be connected as close as possible
between DV+ and DGND (pins 16 and 15). It is not
necessary to use a separate supply or run separate
traces to DV+. If SYNC is disabled, leave DV+ open. ___________________Chip Topography
Do not open DGND.
Minimize the trace area around COSC (and the ground GND REF V- OUT
plane area under COSC) to reduce parasitic capaci-
tance, and surround this trace with ground to prevent AO GND
coupling with other signals. Take similar precautions
with DADJ, FADJ, and IIN. Place CF so its connection
to the ground plane is close to pin 6 (GND). V+
__________Applications Information A1 DV+
Frequency Synthesizer DGND
COSC
Figure 6 shows a frequency synthesizer that produces
accurate and stable sine, square, or triangle waves with 0.118"
a frequency range of 8kHz to 16.383MHz in 1kHz incre- (2.997mm)
ments. A Motorola MC145151 provides the crystal-con-
trolled oscillator, the ÷N circuit, and a high-speed phase
detector. The manual switches set the output frequency; SYNC
GND
opening any switch increases the output frequency.
Each switch controls both the ÷N output and an DADJ PDI
MX7541 12-bit DAC, whose output is converted to a cur-
rent by using both halves of the MAX412 op amp. This FADJ GND IIN GND PDO
current goes to the MAX038 IIN pin, setting its coarse 0.106"
frequency over a very wide range. (2.692mm)
Fine frequency control (and phase lock) is achieved
from the MC145151 phase detector through the differ- TRANSISTOR COUNT: 855
ential amplifier and lowpass filter, U5. The phase detec- SUBSTRATE CONNECTED TO GND
16 ______________________________________________________________________________________